1. Field of the Invention
The present invention relates to a semiconductor integrated circuit whose interface section is tested and a test system for testing the semiconductor integrated circuit.
2. Background Art
A semiconductor integrated circuit has a pin section and an interface section in addition to internal circuits. The interface section generates operation signals for causing operation of the internal circuits by decoding and amplifying input signals that are input via the pin section, and outputs, to an outside, via the pin section, data that are read from the internal circuits.
With the increase in arithmetic processing speed, recent semiconductor integrated circuits are required to operate at a high speed in responding to signals that are input from an external circuit. Particularly, in semiconductor integrated circuits that operate in synchronism with an external clock, an operation frequency has increased steadily. Input/output specification values of the interface section such as a setup time, a hold time, and an access time between an external clock and each control signal have become increasingly small.
With the above tendency, in test systems for testing whether or not the timing of a signal that is input to or output from the interface section via each pin is normal, it is important to adjust, with high accuracy, timing deviations (skews) of test signals that are input or output between a test apparatus and the semiconductor integrated circuit to decrease the skews (de-skewing). For example, where a setup time should be shorter than several hundreds of picoseconds in a product specification, to enable a correct test, the test system should have skew accuracy of several tens of picoseconds or less.
A test on the interface section is performed for a semiconductor integrated circuit for which it has been confirmed in advance with slow timing that logic operations are performed normally. First, in pin electronics of the test apparatus, a common reference comparator compares and checks a waveform format and timing for each pin of the pin section of a device to be tested. Then, on the basis of detection results, de-skewing is performed by finely adjusting variable delay circuits in a timing generator and the pin electronics of the test apparatus, whereby a setup time, a hold time, and an access time are set strictly. Then, the semiconductor integrated circuit as the device to be tested is caused to operate with the same logic scheme as in ordinary operation and with proper input timing and whether the device to be tested operates normally is judged on the basis of its response results.
A test system is composed of a general-purpose test apparatus and a dedicated board on which a device to be tested in to be mounted. The dedicated board complies with the specification of the device to be tested. Various kinds of devices can be tested by exchanging dedicated boards. Devices to be tested are interchanged automatically by a handler. Therefore, the test apparatus and the device to be tested are distant from each other and are connected to each other by coaxial cables or wiring patterns on a circuit board. In this case, designing has been made so that impedance matching is attained between all the related terminals and lines, that is, between driver outputs of the pin electronics and the wiring patterns or coaxial cables. The test apparatus is provided with complex adjustment mechanisms that are necessary for adjustment of timing errors of the order of tens of picoseconds.
In an actual test, whether the interface section operates normally is judged on the basis of response results of internal operation of a device to be tested. Therefore, the waveform format and the timing vary from one pin to another. However, de-skewing is performed by using typical conditions, that is, conditions of a certain waveform format, timing, etc. Therefore, in an actual test, there is a possibility that a subtle timing error occurs in a signal at each terminal of a device to be tested.
As compared with this, in de-skewing and an actual test, the accuracy of timing can be kept high by giving the same waveform to all signals including a reference clock. However, ordinary devices to be tested are inoperative in such a condition.
Additionally, coaxial cables etc. have errors in impedance. Therefore, if a test apparatus and a device to be tested are distant from each other and long wiring is used to connect those, there may occur disturbances between signal propagation delays and waveform disorders, which are factors of lowering the accuracy of timing. As a result, there is a possibility that a signal has a subtle timing error at each terminal of the device to be tested even if de-skewing is performed in the test apparatus.
One measure for solving the above problem is a method that an auxiliary test apparatus is used to enable timing adjustments in the vicinity of a device to be tested. However, the circuits of such an auxiliary test apparatus should be complex to accommodate various kinds of waveform formats and timing.